Consider an NPN transistor amplifier in the common-emitter configuration. The current gain of the transistor is 100. If the collector current changes by 1 mA, what will be the change in emitter current?
1. 1.1 mA                     

2. 1.01 mA

3. 0.01 mA                   

4. 10 mA

In a common base amplifier the phase difference between the input signal voltage and the output voltage is

(1) 0                     

(2) $\mathrm{\pi }/4$

(3)$\mathrm{\pi }/2$                  

(4) $\mathrm{\pi }$

In NPN transistor the collector current is 10 mA. If 90% of electrons emitted reach the collector, then

(1) Emitter current will be 9 mA

(2) Emitter current will be 11.1 mA

(3) Base current will be 0.1 mA

(4) Base current will be 0.01 mA

In a transistor in CE configuration, the ratio of power gain to voltage gain is 
(1) $\mathrm{\alpha }$                                     

(2) $\mathrm{\beta }/\mathrm{\alpha }$ 

(3) $\mathrm{\beta \alpha }$                                     

(4) $\mathrm{\beta }$ 

Given below are symbols for some logic gates

The XOR gate and NOR gate respectively are 
(a) 1 and 2                  (b) 2 and 3
(c) 3 and 4                  (d) 1 and 4

Given below are four logic gate symbol (figure). Those for OR, NOR and NAND are respectively 

(a) 1, 4, 3                     (b) 4, 1, 2
(c) 1, 3, 4                     (d) 4, 2, 1

The following truth table corresponds to the logic gate

A  0  0  1  1
B  0  1  0  1
X  0  1  1  1

(1) NAND                     

(2) OR

(3) AND                       

(4) XOR

The combination of ‘NAND’ gates shown here under (figure) are equivalent to

1. An OR gate and an AND gate respectively
2. An AND gate and a NOT gate respectively
3. An AND gate and an OR gate respectively
4. An OR gate and a NOT gate respectively.

A truth table is given below. Which of the following has this type of truth table 

A  0  1  0  1
B  0  0  1  1
y  1  0  0  0

(1) XOR gate

(2) NOR gate

(3) AND gate

(4) OR gate

For the given combination of gates, if the logic states of inputs A, B, C are as follows A = B = C = 0 and A = B = 1, C = 0 then the logic states of output D are

(1) 0, 0

(2) 0, 1

(3) 1, 0

(4) 1, 1